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IR2277S/IR2177S (PbF)
AC Electrical Characteristics
V BIAS (V CC , V BS ) = 15V unless otherwise specified. Temp=27°C.
Symbol
f sync
Definition
PWM frequency
PO
OUT
Min.
4
8
Typ.
Max.
20
20
Units
kHz
Test
Conditions
f out
BW
GD
Throughput
Bandwidth (@ -3 dB)
Group Delay (input filter)
2 ? f sync
f sync
1
4 ? f sync
ksample/sec
kHz
μs
D min
D max
Minimum Duty Cycle (Note 1)
Maximum Duty Cycle (Note 1)
10
30
%
%
V in =+V inmax
V in =-V inmin
t dOCon
T OCoff
C load
SL OUT
t settl
De-bounce time of OC
Time to reset OC forcing PO
Analog output load capacitor
Analog output (OUT) Slew Rate
Output settling time (1%)
2.7
0
0.2
5
3.5
4.7
0.5
50
1
30
μs
μs
nF
V/μs
μs
See Figure 4
See Figure 4
NOTE 2
C out ≤ 5 nF
C out ≤ 5 nF
MD
Measure Delay
0 . 30
2 ? f sync
μs
SR
Step response (max time to reach
steady state) for PO output
0 . 51
f sync
1 . 3
f sync
μs
See
Figure 5
SR OUT
Step response (max time to reach
steady state) for OUT output
0.51
f sync
+ t settl
1 . 3
f sync
+ t settl
μs
See
Figure 5
Note 1: negative logic, see Figure 4 on page 7
Note 2: Cload < 5 nF avoids overshoot
6
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